FPGA-based High-precision MCU testing using pattern latching and DDLL
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Date
2025-07-25
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
IEEE
Abstract
Performance testing of microcontrollers (MCUs) is very crucial especially when it comes to safety critical systems such as those in automotive electronics field that will require high accuracy and reliability. One of the essential criteria for performance testing are results checking for getting the maximum possible clock frequency of the MCU possible to influence the automobile units’ efficiency. The traditional method of testing using the ring oscillator approach might not be sufficient in giving MCU performance. To this, the system under consideration includes a pattern latching algorithm with an included configurable ring oscillator. The utilization of a clocked latch with a synchronous gate is used to synchronize ring oscillator circuits so as to do precise pattern analysis. The system makes use of a digital delay locked loop (DDLL) to provide high accuracy when measuring performance by dynamically compensating for delays. Such a strategy increases the validity of performance screening, with improved estimation of the MCU’s operating abilities in adverse conditions.
Description
Keywords
Ring oscillators, Performance evaluation, Accuracy, Heuristic algorithms, Delays, Reliability, Phase locked loops, Pattern analysis, Testing, Clocks
Citation
Arunkumar, K., Vani, R., & Ali, G. (2025, June). FPGA-based High-precision MCU testing using pattern latching and DDLL. In 2025 6th International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV): 1798-1803.